1. Field of the Invention
The present invention relates to a complex multiplication circuit for multiplying a complex input signal by a complex multiplier and a filter circuit using the multiplication circuit.
2. Description of the Related Art
A complex filter is used for an orthogonal transformation such as quadrature detection and for filtering an orthogonal signal in an orthogonal space. A channel filter is proposed in the Technical Report of the Institute of Electronics, Information and Communication Engineers MW96-219 (February 1997), which delays an orthogonal signal, multiplies the delayed signal by a complex multiplier and adds the multiplication result to the original orthogonal signal.
A complex multiplication circuit is the main device for the filter of complex multiplier. There are some digital signal processors (DSP) for complex-multiplier filter on the market, for example, part number PDSP16112 by Plessy Semiconductors Inc., HSP43168 by Harris Semiconductor Ion and so forth.
FIG. 7 is a block diagram of the conventional complex multiplication circuit consisting of multipliers 101 to 104 and adders 105 and 106. A complex input signal (x+jy) is multiplied by a complex multiplier (a+jb) so as to output an multiplication result P=P.sub.R +jP.sub.I as follows. ##EQU1## The multiplication circuit performs multiplications ax, ay, bx and by by the multipliers 101, 102, 103 and 104. The outputs of multiplier 104 are subtracted from the output of the multiplier 101 by an adder 105, the output of multiplier 102 is added to the output of the multiplier 103 by an adder 106.
FIG. 8 is a circuit diagram of complex-multiplier ester. The input x in held by a series of sampling and holding circuits 61 to 63. The input y is held by a series of sampling and holding circuits 68 to 70. The held input x is multiplied by multipliers a0, to aN-1 in the multipliers 111 to 113 and multiplied by multipliers b0 to bN-1 in the multipliers 115 to 117. The held input y is multiplied by multipliers a0 to aN-1 in the multipliers 119 to 121 and multiplied by multipliers b0 to bN-1 in the multipliers 123 to 125.
Outputs from the multipliers 111 to 113 are summed by an adder 114, and outputs from the multipliers 115, to 117 are summed by an adder 118. Outputs from the multipliers 119 to 121 are summed by an adder 122, and outputs from the multipliers 123 to 125 are summed by an adder 126. The sum outputted from the adder 126 is subtracted from the sum outputted from the adder 114 to generate the real output P.sub.R (n). The sum outputted from the adder 118 is added to the sum outputted from the adder 122 to generate the imaginary output P.sub.I (n).
P.sub.R (n) and P.sub.I (n) are calculated as in the equations (2) and (3). ##EQU2## Here, x(i) and y(i) (i=0, 1, 2, . . . , N-1) are with signals held at the ith timing dock.
The multiplication circuit above is large in size because it consist of two very large multipliers. This causes a serious problem in applications which require small size, light weight and low power consumption.
The DSP by Harris processes the multiplication using a time-sharing sequence which decreasing the size of the circuit. However, the process also decreases the speed.